EP3C120F484C7 Datasheet, PDF (102/274 Pages) Altera Corporation – Cyclone III Device Handbook

6–4
Chapter 6: I/O Features in the Cyclone III Device Family
I/O Element Features
Slew Rate Control
The output buffer for each Cyclone III device family I/O pin provides optional
programmable output slew-rate control. The Quartus II software allows three settings
for programmable slew rate control—0, 1, and 2—where 0 is the slow slew rate and 2
is the fast slew rate. The default setting is 2. A faster slew rate provides high-speed
transitions for high-performance systems. However, these fast transitions may
introduce noise transients in the system. A slower slew rate reduces system noise, but
adds a nominal delay to rising and falling edges. Because each I/O pin has an
individual slew-rate control, you can specify the slew rate on a pin-by-pin basis. The
slew-rate control affects both the rising and falling edges. Slew rate control is available
for single-ended I/O standards with current strength of 8 mA or higher.
1 You cannot use the programmable slew rate feature when using OCT with or without
calibration.
1 You cannot use the programmable slew rate feature when using the 3.0-V PCI,
3.0-V PCI-X, 3.3-V LVTTL, and 3.3-V LVCMOS I/O standards. Only fast slew rate
(default) setting is available.
Open-Drain Output
The Cyclone III device family provides an optional open-drain (equivalent to an
open-collector) output for each I/O pin. This open-drain output enables the device to
provide system-level control signals (for example, interrupt and write enable signals)
that are asserted by multiple devices in your system.
Bus Hold
Each Cyclone III device family user I/O pin provides an optional bus-hold feature.
The bus-hold circuitry holds the signal on an I/O pin at its last-driven state. Because
the bus-hold feature holds the last-driven state of the pin until the next input signal is
present, an external pull-up or pull-down resistor is not necessary to hold a signal
level when the bus is tri-stated.
The bus-hold circuitry also pulls undriven pins away from the input threshold
voltage in which noise can cause unintended high-frequency switching. You can select
this feature individually for each I/O pin. The bus-hold output drives no higher than
V_CCIO to prevent overdriving signals.
1 If you enable the bus-hold feature, the device cannot use the programmable pull-up
option. Disable the bus-hold feature when the I/O pin is configured for differential
signals. Bus-hold circuitry is not available on dedicated clock pins.
Bus-hold circuitry is only active after configuration. When going into user mode, the
bus-hold circuit captures the value on the pin present at the end of configuration.
f For the specific sustaining current for each V_CCIO voltage level driven through the
resistor and for the overdrive current used to identify the next driven input level, refer
to the Cyclone III Device Data Sheet and Cyclone III LS Device Data Sheet chapters.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation