|
EP3C120F484C7 Datasheet, PDF (44/274 Pages) Altera Corporation – Cyclone III Device Handbook | |||
|
◁ |
3â10
Chapter 3: Memory Blocks in the Cyclone III Device Family
Memory Modes
Table 3â3. Cyclone III Device Family M9K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 2 of 2)
Read Port
512 Ã 16
256 Ã 32
1024 Ã 9
512 Ã 18
256 Ã 36
8192 Ã 1
v
v
â
â
â
4096 Ã 2
v
v
â
â
â
2048 Ã 4
v
v
â
â
â
Write Port
1024 Ã 8
v
v
â
â
â
512 Ã 16
v
v
â
â
â
256 Ã 32
v
v
â
â
â
1024 Ã 9
â
â
v
v
v
512 Ã 18
â
â
v
v
v
256 Ã 36
â
â
v
v
v
In simple dual-port mode, M9K memory blocks support separate wren and rden
signals. You can save power by keeping the rden signal low (inactive) when not
reading. Read-during-write operations to the same address can either output âDonât
Careâ data at that location or output âOld Dataâ. To choose the desired behavior, set
the Read-During-Write option to either Donât Care or Old Data in the RAM
MegaWizard Plug-In Manager in the Quartus II software. For more information about
this behavior, refer to âRead-During-Write Operationsâ on page 3â15.
Figure 3â10 shows the timing waveforms for read and write operations in simple
dual-port mode with unregistered outputs. Registering the outputs of the RAM
simply delays the q output by one clock cycle.
Figure 3â10. Cyclone III Device Family Simple Dual-Port Timing Waveforms
wrclock
wren
wraddress an-1
an
a0
data din-1
din
rdclock
rden
rdaddress
bn
b0
a1
a2
b1
a3
a4
a5
a6
din4
din5
din6
b2
b3
q (asynch) doutn-1
doutn
dout0
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
|
▷ |