EP3C120F484C7 Datasheet, PDF (193/274 Pages) Altera Corporation – Cyclone III Device Handbook

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
9–35
PS Configuration Using an External Host
In the PS configuration scheme, you can use an intelligent host such as MAX II or
microprocessor that controls the transfer of configuration data from a storage device,
such as flash memory, to the target Cyclone III device family. You can store the
configuration data in .rbf, .hex, or .ttf format.
Figure 9–14 shows the configuration interface connections between a Cyclone III
device family and an external host device for a single-device configuration.
Figure 9–14. Single-Device PS Configuration Using an External Host
Memory
Cyclone III
V_CCIO(1) V_CCIO(1) Device Family
ADDR DATA[0]
10 kΩ 10 kΩ
MSEL[3..0]
(3)
External Host
(MAX II Device or
Microprocessor)
GND
CONF_DONE
nSTATUS
nCE
nCEO N.C. (2)
DATA[0] (4)
nCONFIG
DCLK (4)
Notes to Figure 9–14:
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for the device. V_CC must be high
enough to meet the V_IH specification of the I/O on the device and the external host.
(2) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0],
refer to Table 9–7 on page 9–11. Connect the MSEL pins directly to V_CCA or ground.
(4) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[0] and DCLK must fit the maximum overshoot
equation outlined in “Configuration and JTAG Pin I/O Requirements” on page 9–7.
To begin configuration, the external host device must generate a low-to-high
transition on the nCONFIG pin. When nSTATUS is pulled high, the external host device
must place the configuration data one bit at a time on the DATA[0]pin. If you are using
configuration data in a .rbf, .ttf, or .hex file, you must first send the LSB of each data
byte. For example, if the .rbf contains the byte sequence 02 1B EE 01 FA, the serial
bitstream you must send to the device is:
0100-0000 1101-1000 0111-0111 1000-0000 0101-1111
Cyclone III device family receives configuration data on the DATA[0]pin and the clock
is received on the DCLK pin. Data is latched into the device on the rising edge of DCLK.
Data is continuously clocked into the target device until CONF_DONE goes high and the
device enters the initialization state.
1 Two DCLK falling edges are required after CONF_DONE goes high to begin device
initialization.
The INIT_DONE pin is released and pulled high when initialization is complete. The
external host device must be able to detect this low-to-high transition which signals
the device has entered user mode. When initialization is complete, the device enters
user mode. In user mode, the user I/O pins no longer have weak pull-up resistors and
function as assigned in your design.
August 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1