EP20K400EFC672-1X Datasheet, PDF (79/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Table 42. EP20K400 f_MAX Timing Parameters
Symbol
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Units
t_SU
t_H
t_CO
t_LUT
t_ESBRC
t_ESBWC
t_ESBWESU
t_ESBDATASU
t_ESBDATAH
t_ESBADDRSU
t_ESBDATACO1
t_ESBDATACO2
t_ESBDD
t_PD
t_PTERMSU
t_PTERMCO
t_F1-4
t_F5-20
t_F20+
t_CH
t_CL
t_CLRP
t_PREP
t_ESBCH
t_ESBCL
t_ESBWP
t_ESBRP
Min
Max
Min
Max
Min
Max
0.1
0.3
0.6
ns
0.5
0.8
0.9
ns
0.1
0.4
0.6
ns
1.0
1.2
1.4
ns
1.7
2.1
2.4
ns
5.7
6.9
8.1
ns
3.3
3.9
4.6
ns
2.2
2.7
3.1
ns
0.6
0.8
0.9
ns
2.4
2.9
3.3
ns
1.3
1.6
1.8
ns
2.5
3.1
3.6
ns
2.5
3.3
3.6
ns
2.5
3.1
3.6
ns
1.7
2.1
2.4
ns
1.0
1.2
1.4
ns
0.4
0.5
0.6
ns
2.6
2.8
2.9
ns
3.7
3.8
3.9
ns
2.0
2.5
3.0
ns
2.0
2.5
3.0
ns
0.5
0.6
0.8
ns
0.5
0.5
0.5
ns
2.0
2.5
3.0
ns
2.0
2.5
3.0
ns
1.5
1.9
2.2
ns
1.0
1.2
1.4
ns
Tables 43 through 48 show the I/O external and external bidirectional
timing parameter values for EP20K100, EP20K200, and EP20K400
APEX 20K devices.
Altera Corporation
79