EP20K400EFC672-1X Datasheet, PDF (52/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Notes to Table 16:
(1) To implement the ClockLock and ClockBoost circuitry with the Quartus II software, designers must specify the
input frequency. The Quartus II software tunes the PLL in the ClockLock and ClockBoost circuitry to this frequency.
The f_CLKDEV parameter specifies how much the incoming clock can differ from the specified frequency during
device operation. Simulation does not reflect this parameter.
(2) Twenty-five thousand parts per million (PPM) equates to 2.5% of input clock period.
(3) During device configuration, the ClockLock and ClockBoost circuitry is configured before the rest of the device. If
the incoming clock is supplied during configuration, the ClockLock and ClockBoost circuitry locks during
configuration because the t_LOCK value is less than the time required for configuration.
(4) The t_JITTER specification is measured under long-term observation.
Tables 17 and 18 summarize the ClockLock and ClockBoost parameters
for APEX 20KE devices.
Table 17. APEX 20KE ClockLock & ClockBoost Parameters Note (1)
Symbol
t_R
t_F
t _INDUTY
t _INJITTER
Parameter
Input rise time
Input fall time
Input duty cycle
Input jitter peak-to-peak
Conditions Min
40
t_OUTJITTER
Jitter on ClockLock or ClockBoost-
generated clock
t_OUTDUTY
Duty cycle for ClockLock or
45
ClockBoost-generated clock
t_LOCK (2)_, (3) Time required for ClockLock or
ClockBoost to acquire lock
Typ
Max
Unit
5
ns
5
ns
60
%
2% of input peak-to-
period
peak
0.35% of
RMS
output period
55
%
40
µs
52
Altera Corporation