EP20K400EFC672-1X Datasheet, PDF (1/117 Pages) Altera Corporation – Programmable Logic Device Family

March 2004, ver. 5.1
APEX 20K
Programmable Logic
Device Family
Data Sheet
Features
■ Industry’s first programmable logic device (PLD) incorporating
system-on-a-programmable-chip (SOPC) integration
– MultiCore^TM architecture integrating look-up table (LUT) logic,
product-term logic, and embedded memory
– LUT logic used for register-intensive functions
– Embedded system block (ESB) used to implement memory
functions, including first-in first-out (FIFO) buffers, dual-port
RAM, and content-addressable memory (CAM)
– ESB implementation of product-term logic used for
combinatorial-intensive functions
■ High density
– 30,000 to 1.5 million typical gates (see Tables 1 and 2)
– Up to 51,840 logic elements (LEs)
– Up to 442,368 RAM bits that can be used without reducing
available logic
– Up to 3,456 product-term-based macrocells
Table 1. APEX 20K Device Features Note (1)
Feature
Maximum
system
gates
Typical
gates
LEs
ESBs
Maximum
RAM bits
Maximum
macrocells
Maximum
user I/O
pins
EP20K30E EP20K60E
113,000 162,000
30,000
1,200
12
24,576
192
128
60,000
2,560
16
32,768
256
196
EP20K100
263,000
100,000
4,160
26
53,248
416
252
EP20K100E EP20K160E
263,000
404,000
100,000
4,160
26
53,248
416
246
160,000
6,400
40
81,920
640
316
EP20K200
526,000
200,000
8,320
52
106,496
832
382
EP20K200E
526,000
200,000
8,320
52
106,496
832
376
Altera Corporation
1
DS-APEX20K-5.1