EP20K400EFC672-1X Datasheet, PDF (33/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Input/Output Clock Mode
The input/output clock mode contains two clocks. One clock controls all
registers for inputs into the ESB: data input, WE, RE, read address, and
write address. The other clock controls the ESB data output registers. The
ESB also supports clock enable and asynchronous clear signals; these
signals also control the reading and writing of registers independently.
Input/output clock mode is commonly used for applications where the
reads and writes occur at the same system frequency, but require different
clock enable signals for the input and output registers. Figure 21 shows
the ESB in input/output clock mode.
Figure 21. ESB in Input/Output Clock Mode
Dedicated Inputs &
Global Signals
Dedicated Clocks
Note (1)
data[ ]
2 or 4 4
(2)
DQ
ENA
rdaddress[ ]
DQ
ENA
wraddress[ ]
rden
DQ
ENA
wren
outclken
DQ
ENA
inclken
inclock
outclock
DQ
ENA
Write
Pulse
Generator
RAM/ROM
128 × 16
256 × 8
Data In
512 × 4
1,024 × 2
2,048 × 1
Data Out
Read Address
DQ
ENA
Write Address
Read Enable
Write Enable
to MegaLAB,
FastTrack &
Local
Interconnect
Notes to Figure 21:
(1) All registers can be cleared asynchronously by ESB local interconnect signals, global signals, or the chip-wide reset.
(2) APEX 20KE devices have four dedicated clocks.
Altera Corporation
Single-Port Mode
The APEX 20K ESB also supports a single-port mode, which is used when
simultaneous reads and writes are not required. See Figure 22.
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