EP20K400EFC672-1X Datasheet, PDF (76/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Table 39. APEX 20KE External Bidirectional Timing Parameters Note (1)
Symbol
Parameter
t_INSUBIDIR
Setup time for bidirectional pins with global clock at LAB adjacent Input
Register
t_INHBIDIR
Hold time for bidirectional pins with global clock at LAB adjacent Input
Register
t_OUTCOBIDIR
Clock-to-output delay for bidirectional pins with global clock at IOE output
register
t_XZBIDIR
t_ZXBIDIR
t_INSUBIDIRPLL
Synchronous Output Enable Register to output buffer disable delay
Synchronous Output Enable Register output buffer enable delay
Setup time for bidirectional pins with PLL clock at LAB adjacent Input
Register
t_INHBIDIRPLL
Hold time for bidirectional pins with PLL clock at LAB adjacent Input
Register
t_{OUTCOBIDIRPLL}
Clock-to-output delay for bidirectional pins with PLL clock at IOE output
register
t_XZBIDIRPLL
Synchronous Output Enable Register to output buffer disable delay with
PLL
t_ZXBIDIRPLL
Synchronous Output Enable Register output buffer enable delay with PLL
Note to Tables 38 and 39:
(1) These timing parameters are sample-tested only.
Conditions
C1 = 10 pF
C1 = 10 pF
C1 = 10 pF
C1 = 10 pF
C1 = 10 pF
C1 = 10 pF
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