EP20K400EFC672-1X Datasheet, PDF (13/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Logic Element
The LE, the smallest unit of logic in the APEX 20K architecture, is compact
and provides efficient logic usage. Each LE contains a four-input LUT,
which is a function generator that can quickly implement any function of
four variables. In addition, each LE contains a programmable register and
carry and cascade chains. Each LE drives the local interconnect, MegaLAB
interconnect, and FastTrack Interconnect routing structures. See Figure 5.
Figure 5. APEX 20K Logic Element
Carry-In
LAB-wide LAB-wide
Synchronous Synchronous
Load
Clear
Cascade-In
data1
data2
data3
data4
Look-Up
Table
(LUT)
Carry
Chain
Cascade
Chain
Synchronous
Load & Clear
Logic
labclr1
labclr2
Chip-Wide
Reset
labclk1
labclk2
labclkena1
labclkena2
Asynchronous
Clear/Preset/
Load Logic
Clock &
Clock Enable
Select
Carry-Out
Cascade-Out
Register Bypass
Packed
Register Select
Programmable
Register
PRN
DQ
ENA
CLRN
To FastTrack Interconnect,
MegaLAB Interconnect,
or Local Interconnect
To FastTrack Interconnect,
MegaLAB Interconnect,
or Local Interconnect
Each LE’s programmable register can be configured for D, T, JK, or SR
operation. The register’s clock and clear control signals can be driven by
global signals, general-purpose I/O pins, or any internal logic. For
combinatorial functions, the register is bypassed and the output of the
LUT drives the outputs of the LE.
Altera Corporation
13