EP20K400EFC672-1X Datasheet, PDF (36/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
f For more information on APEX 20KE devices and CAM, see Application
Note 119 (Implementing High-Speed Search Applications with APEX CAM).
Driving Signals to the ESB
ESBs provide flexible options for driving control signals. Different clocks
can be used for the ESB inputs and outputs. Registers can be inserted
independently on the data input, data output, read address, write
address, WE, and RE signals. The global signals and the local interconnect
can drive the WE and RE signals. The global signals, dedicated clock pins,
and local interconnect can drive the ESB clock signals. Because the LEs
drive the local interconnect, the LEs can control the WE and RE signals and
the ESB clock, clock enable, and asynchronous clear signals. Figure 24
shows the ESB control signal generation logic.
Figure 24. ESB Control Signal Generation
Dedicated
Clocks
2 or 4 (1)
Global
4
Signals
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
INCLKENA
OUTCLKENA
RDEN WREN INCLOCK
OUTCLOCK
INCLR OUTCLR
Note to Figure 24:
(1) APEX 20KE devices have four dedicated clocks.
An ESB is fed by the local interconnect, which is driven by adjacent LEs
(for high-speed connection to the ESB) or the MegaLAB interconnect. The
ESB can drive the local, MegaLAB, or FastTrack Interconnect routing
structure to drive LEs and IOEs in the same MegaLAB structure or
anywhere in the device.
36
Altera Corporation