EP20K400EFC672-1X Datasheet, PDF (39/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Figure 25. APEX 20K Bidirectional I/O Registers Note (1)
Row, Column,
2 Dedicated
or Local Interconnect Clock Inputs
4 Dedicated Peripheral Control
Inputs
Bus
OE Register
DQ
VCC
ENA
CLRN
OE[7..0]
Chip-Wide Reset
VCC
Chip-Wide
Output Enable
12
2 _VCC
CLK[1..0]
CLK[3..2]
ENA[5..0]
Input Pin to
Core Delay
Core to Output
Register Delay
Input Pin to Input
Register Delay
VCC
Output Register
DQ
ENA
CLRN
Output Register
t CODelay
Open-Drain
Output
Slew-Rate
Control
CLRn[1..0]
VCC
VCC
Chip-Wide
Reset _{Input Register}
DQ
VCC
ENA
CLRN
VCCIO
Optional
PCI Clamp
Chip-Wide
Reset
Note to Figure 25:
(1) The output enable and input registers are LE registers in the LAB adjacent to the bidirectional pin.
Altera Corporation
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