EP20K400EFC672-1X Datasheet, PDF (61/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Table 25. APEX 20K 5.0-V Tolerant Device DC Operating Conditions (Part 2 of 2) Notes (2), (7), (8)
Symbol
Parameter
Conditions
Min
V _OL
I_I
I _OZ
I _CC0
R _CONF
3.3-V low-level TTL output voltage I_OL = 12 mA DC,
V_CCIO = 3.00 V (11)
3.3-V low-level CMOS output
voltage
I_OL = 0.1 mA DC,
V_CCIO = 3.00 V (11)
3.3-V low-level PCI output voltage I_OL = 1.5 mA DC,
V_CCIO = 3.00 to 3.60 V
(11)
2.5-V low-level output voltage
I_OL = 0.1 mA DC,
V_CCIO = 2.30 V (11)
I_OL = 1 mA DC,
V_CCIO = 2.30 V (11)
I_OL = 2 mA DC,
V_CCIO = 2.30 V (11)
Input pin leakage current
V_I = 5.75 to –0.5 V
–10
Tri-stated I/O pin leakage current V_O = 5.75 to –0.5 V
–10
V_CC supply current (standby)
V_I = ground, no load, no
(All ESBs in power-down mode) toggling inputs, -1 speed
grade (12)
V_I = ground, no load, no
toggling inputs,
-2, -3 speed grades (12)
Value of I/O pin pull-up resistor V_CCIO = 3.0 V (13)
20
before and during configuration _{VCCIO = 2.375 V (13)}
30
Typ
Max
Unit
0.45
V
0.2
V
0.1 × V_CCIO
V
0.2
V
0.4
V
0.7
V
10
µA
10
µA
10
mA
5
mA
50
W
80
W
Altera Corporation
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