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EP20K400EFC672-1X Datasheet, PDF (3/117 Pages) Altera Corporation – Programmable Logic Device Family | |||
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Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
â Flexible clock management circuitry with up to four phase-locked
loops (PLLs)
â Built-in low-skew clock tree
â Up to eight global clock signals
â ClockLock® feature reducing clock delay and skew
â ClockBoost® feature providing clock multiplication and division
â ClockShiftTM programmable clock phase and delay shifting
â Powerful I/O features
â Compliant with peripheral component interconnect Special
Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2 for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits
â Support for high-speed external memories, including DDR
SDRAM and ZBT SRAM (ZBT is a trademark of Integrated
Device Technology, Inc.)
â Bidirectional I/O performance (tCO + tSU) up to 250 MHz
â LVDS performance up to 840 Mbits per channel
â Direct connection from I/O pins to local interconnect providing
fast tCO and tSU times for complex logic
â MultiVolt I/O interface support to interface with 1.8-V, 2.5-V,
3.3-V, and 5.0-V devices (see Table 3)
â Programmable clamp to VCCIO
â Individual tri-state output enable control for each pin
â Programmable output slew-rate control to reduce switching
noise
â Support for advanced I/O standards, including low-voltage
differential signaling (LVDS), LVPECL, PCI-X, AGP, CTT, stub-
series terminated logic (SSTL-3 and SSTL-2), Gunning
transceiver logic plus (GTL+), and high-speed terminated logic
(HSTL Class I)
â Pull-up on I/O pins before and during configuration
â Advanced interconnect structure
â Four-level hierarchical FastTrack® Interconnect structure
providing fast, predictable interconnect delays
â Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
â Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
â Interleaved local interconnect allows one LE to drive 29 other
LEs through the fast local interconnect
â Advanced packaging options
â Available in a variety of packages with 144 to 1,020 pins (see
Tables 4 through 7)
â FineLine BGA® packages maximize board space efficiency
â Advanced software support
â Software design support and automatic place-and-route
provided by the Altera® Quartus® II development system for
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