EP20K400EFC672-1X Datasheet, PDF (50/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Figure 30. Specifications for the Incoming & Generated Clocks Note (1)
f _CLK1,f _CLK2,
f _CLK4
t _INDUTY
t _I + t _CLKDEV
Input
Clock
t_R
t_F
t _OUTDUTY
t_O
t _I + t _INCLKSTB
ClockLock
Generated
Clock
t_O
t_O + t _JITTER t_O t _JITTER
Note to Figure 30:
(1) The tI parameter refers to the nominal input clock period; the tO parameter refers
to the nominal output clock period.
Table 15 summarizes the APEX 20K ClockLock and ClockBoost
parameters for -1 speed-grade devices.
Table 15. APEX 20K ClockLock & ClockBoost Parameters for -1 Speed-Grade Devices (Part 1 of 2)
Symbol
Parameter
Min
f_OUT
Output frequency
25
f_CLK1 (1)
Input clock frequency (ClockBoost clock
25
multiplication factor equals 1)
f_CLK2
Input clock frequency (ClockBoost clock
16
multiplication factor equals 2)
f_CLK4
Input clock frequency (ClockBoost clock
10
multiplication factor equals 4)
t_OUTDUTY
Duty cycle for ClockLock/ClockBoost-generated
40
clock
f_CLKDEV
Input deviation from user specification in the
Quartus II software (ClockBoost clock
multiplication factor equals 1) (2)
t_R
t_F
t_LOCK
Input rise time
Input fall time
Time required for ClockLock/ClockBoost to
acquire lock (4)
Max
180
180 (1)
90
48
60
25,000 (3)
Unit
MHz
MHz
MHz
MHz
%
PPM
5
ns
5
ns
10
µs
50
Altera Corporation