EP20K400EFC672-1X Datasheet, PDF (11/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Logic Array Block
Each LAB consists of 10 LEs, the LEs’ associated carry and cascade chains,
LAB control signals, and the local interconnect. The local interconnect
transfers signals between LEs in the same or adjacent LABs, IOEs, or ESBs.
The Quartus II Compiler places associated logic within an LAB or
adjacent LABs, allowing the use of a fast local interconnect for high
performance. Figure 3 shows the APEX 20K LAB.
APEX 20K devices use an interleaved LAB structure. This structure allows
each LE to drive two local interconnect areas. This feature minimizes use
of the MegaLAB and FastTrack interconnect, providing higher
performance and flexibility. Each LE can drive 29 other LEs through the
fast local interconnect.
Figure 3. LAB Structure
Row
Interconnect
MegaLAB Interconnect
LEs drive local
MegaLAB, row,
and column
interconnects.
To/From
Adjacent LAB,
ESB, or IOEs
Local Interconnect
The 10 LEs in the LAB are driven by
two local interconnect areas. These LEs
can drive two local interconnect areas.
Altera Corporation
To/From
Adjacent LAB,
ESB, or IOEs
Column
Interconnect
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