EP20K300EQC240-1 Datasheet, PDF (77/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Tables 40 through 42 show the f_MAX timing parameters for EP20K100,
EP20K200, and EP20K400 APEX 20K devices.
Table 40. EP20K100 f_MAX Timing Parameters
Symbol
-1 Speed Grade
-2 Speed Grade
t_SU
t_H
t_CO
t_LUT
t_ESBRC
t_ESBWC
t_ESBWESU
t_ESBDATASU
t_ESBDATAH
t_ESBADDRSU
t_ESBDATACO1
t_ESBDATACO2
t_ESBDD
t_PD
t_PTERMSU
t_PTERMCO
t_F1-4
t_F5-20
t_F20+
t_CH
t_CL
t_CLRP
t_PREP
t_ESBCH
t_ESBCL
t_ESBWP
t_ESBRP
Min
Max
Min
Max
0.5
0.6
0.7
0.8
0.3
0.4
0.8
1.0
1.7
2.1
5.7
6.9
3.3
3.9
2.2
2.7
0.6
0.8
2.4
2.9
1.3
1.6
2.6
3.1
2.5
3.3
2.5
3.0
2.3
2.6
1.5
1.8
0.5
0.6
1.6
1.7
2.2
2.2
2.0
2.5
2.0
2.5
0.3
0.4
0.5
0.5
2.0
2.5
2.0
2.5
1.6
1.9
1.0
1.3
-3 Speed Grade
Min
Max
0.8
1.0
0.5
1.3
2.4
8.1
4.6
3.1
0.9
3.3
1.8
3.6
3.6
3.6
3.2
2.1
0.7
1.8
2.3
3.0
3.0
0.4
0.5
3.0
3.0
2.2
1.4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Altera Corporation
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