EP20K300EQC240-1 Datasheet, PDF (26/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Figure 13. Product-Term Logic in ESB
Dedicated Clocks
Global Signals
4 2 or 4 (1)
MegaLAB Interconnect
65
From
Adjacent
LAB
9
32
Macrocell
Inputs (1-16)
2
CLK[1..0]
16
2
ENA[1..0]
2
CLRN[1..0]
To Row
and Column
Interconnect
Local
Interconnect
Note to Figure 13:
(1) APEX 20KE devices have four dedicated clocks.
Macrocells
APEX 20K macrocells can be configured individually for either sequential
or combinatorial logic operation. The macrocell consists of three
functional blocks: the logic array, the product-term select matrix, and the
programmable register.
Combinatorial logic is implemented in the product terms. The product-
term select matrix allocates these product terms for use as either primary
logic inputs (to the OR and XOR gates) to implement combinatorial
functions, or as parallel expanders to be used to increase the logic
available to another macrocell. One product term can be inverted; the
Quartus II software uses this feature to perform DeMorgan’s inversion for
more efficient implementation of wide OR functions. The Quartus II
software Compiler can use a NOT-gate push-back technique to emulate an
asynchronous preset. Figure 14 shows the APEX 20K macrocell.
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Altera Corporation