EP20K300EQC240-1 Datasheet, PDF (74/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Note to Tables 32 and 33:
(1) These timing parameters are sample-tested only.
Tables 34 through 37 show APEX 20KE LE, ESB, routing, and functional
timing microparameters for the f_MAX timing model.
Table 34. APEX 20KE LE Timing Microparameters
Symbol
t_SU
t_H
t_CO
t_LUT
Parameter
LE register setup time before clock
LE register hold time after clock
LE register clock-to-output delay
LUT delay for data-in to data-out
Table 35. APEX 20KE ESB Timing Microparameters
Symbol
t_ESBARC
t_ESBSRC
t_ESBAWC
t_ESBSWC
t_ESBWASU
t_ESBWAH
t_ESBWDSU
t_ESBWDH
t_ESBRASU
t_ESBRAH
t_ESBWESU
t_ESBWEH
t_ESBDATASU
t_ESBDATAH
t_ESBWADDRSU
t_ESBRADDRSU
t_ESBDATACO1
t_ESBDATACO2
t_ESBDD
t_PD
t_PTERMSU
t_PTERMCO
Parameter
ESB Asynchronous read cycle time
ESB Synchronous read cycle time
ESB Asynchronous write cycle time
ESB Synchronous write cycle time
ESB write address setup time with respect to WE
ESB write address hold time with respect to WE
ESB data setup time with respect to WE
ESB data hold time with respect to WE
ESB read address setup time with respect to RE
ESB read address hold time with respect to RE
ESB WE setup time before clock when using input register
ESB WE hold time after clock when using input register
ESB data setup time before clock when using input register
ESB data hold time after clock when using input register
ESB write address setup time before clock when using input
registers
ESB read address setup time before clock when using input
registers
ESB clock-to-output delay when using output registers
ESB clock-to-output delay without output registers
ESB data-in to data-out delay for RAM mode
ESB Macrocell input to non-registered output
ESB Macrocell register setup time before clock
ESB Macrocell register clock-to-output delay
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