EP20K300EQC240-1 Datasheet, PDF (68/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
All specifications are always representative of worst-case supply voltage
and junction temperature conditions. All output-pin-timing specifications
are reported for maximum driver strength.
Figure 36 shows the f_MAX timing model for APEX 20K devices.
Figure 36. APEX 20K f_MAX Timing Model
LE
t_SU
t_H
t_CO
t_LUT
ESB
t_ESBRC
t_ESBWC
t_ESBWESU
t_ESBDATASU
t_ESBADDRSU
t_ESBDATACO1
t_ESBDATACO2
t_ESBDD
t_PD
t_PTERMSU
t_PTERMCO
Routing Delay
t _F1—4
t _F5—20
t_F20+
Figure 37 shows the f_MAX timing model for APEX 20KE devices. These
parameters can be used to estimate f_MAX for multiple levels of logic.
Quartus II software timing analysis should be used for more accurate
timing information.
68
Altera Corporation