EP20K300EQC240-1 Datasheet, PDF (53/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Table 18. APEX 20KE Clock Input & Output Parameters (Part 1 of 2) Note (1)
Symbol
Parameter
I/O Standard
f_VCO (4)
Voltage controlled oscillator
operating range
f_CLOCK0
Clock0 PLL output frequency
for internal use
f_CLOCK1
Clock1 PLL output frequency
for internal use
f_{CLOCK0_EXT} Output clock frequency for
external clock0 output
f_{CLOCK1_EXT} Output clock frequency for
external clock1 output
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
GTL+
SSTL-2 Class
I
SSTL-2 Class
II
SSTL-3 Class
I
SSTL-3 Class
II
LVDS
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
GTL+
SSTL-2 Class
I
SSTL-2 Class
II
SSTL-3 Class
I
SSTL-3 Class
II
LVDS
-1X Speed Grade
Min
Max
200
500
1.5
335
20
335
1.5
245
1.5
234
1.5
223
1.5
205
1.5
158
1.5
142
1.5
166
1.5
149
1.5
420
20
245
20
234
20
223
20
205
20
158
20
142
20
166
20
149
20
420
-2X Speed Grade
Min
Max
200
500
Units
MHz
1.5
200 MHz
20
200 MHz
1.5
226 MHz
1.5
221 MHz
1.5
216 MHz
1.5
193 MHz
1.5
157 MHz
1.5
142 MHz
1.5
162 MHz
1.5
146 MHz
1.5
350 MHz
20
226 MHz
20
221 MHz
20
216 MHz
20
193 MHz
20
157 MHz
20
142 MHz
20
162 MHz
20
146 MHz
20
350 MHz
Altera Corporation
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