EP20K300EQC240-1 Datasheet, PDF (34/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Figure 22. ESB in Single-Port Mode
Dedicated Inputs &
Global Signals
Dedicated Clocks
Note (1)
data[ ]
2 or 4 4
(2)
DQ
ENA
address[ ]
wren
outclken
DQ
ENA
inclken
inclock
outclock
DQ
ENA
Write
Pulse
Generator
RAM/ROM
128 × 16
256 × 8
Data In
512 × 4
1,024 × 2
2,048 × 1
Data Out
Address
DQ
ENA
Write Enable
to MegaLAB,
FastTrack &
Local
Interconnect
Notes to Figure 22:
(1) All registers can be asynchronously cleared by ESB local interconnect signals, global signals, or the chip-wide reset.
(2) APEX 20KE devices have four dedicated clocks.
Content-Addressable Memory
In APEX 20KE devices, the ESB can implement CAM. CAM can be
thought of as the inverse of RAM. When read, RAM outputs the data for
a given address. Conversely, CAM outputs an address for a given data
word. For example, if the data FA12 is stored in address 14, the CAM
outputs 14 when FA12 is driven into it.
CAM is used for high-speed search operations. When searching for data
within a RAM block, the search is performed serially. Thus, finding a
particular data word can take many cycles. CAM searches all addresses in
parallel and outputs the address storing a particular word. When a match
is found, a match flag is set high. Figure 23 shows the CAM block
diagram.
34
Altera Corporation