EP20K300EQC240-1 Datasheet, PDF (18/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Figure 8. APEX 20K LE Operating Modes
Normal Mode (1)
Carry-In (3)
data1
data2
data3
data4
Cascade-In
4-Input
LUT
LAB-Wide
Clock Enable (2)
PRN
DQ
ENA
CLRN
Arithmetic Mode
Carry-In
Cascade-Out
Cascade-In
LAB-Wide
Clock Enable (2)
data1
data2
3-Input
LUT
3-Input
LUT
Cascade-Out
Carry-Out
PRN
DQ
ENA
CLRN
LE-Out
LE-Out
LE-Out
LE-Out
Counter Mode
Carry-In
(4)
data1 (5)
data2 (5)
data3 (data)
Cascade-In
LAB-Wide
Synchronous
Clear (6)
LAB-Wide
Synchronous LAB-Wide
Load (6)
Clock Enable (2)
3-Input
LUT
3-Input
LUT
Carry-Out Cascade-Out
PRN
DQ
ENA
CLRN
LE-Out
LE-Out
Notes to Figure 8:
(1) LEs in normal mode support register packing.
(2) There are two LAB-wide clock enables per LAB.
(3) When using the carry-in in normal mode, the packed register feature is unavailable.
(4) A register feedback multiplexer is available on LE1 of each LAB.
(5) The DATA1 and DATA2 input signals can supply counter enable, up or down control, or register feedback signals for
LEs other than the second LE in an LAB.
(6) The LAB-wide synchronous clear and LAB wide synchronous load affect all registers in an LAB.
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Altera Corporation