EP20K300EQC240-1 Datasheet, PDF (54/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Table 18. APEX 20KE Clock Input & Output Parameters (Part 2 of 2) Note (1)
Symbol
Parameter
f_IN
Input clock frequency
I/O Standard
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
GTL+
SSTL-2 Class
I
SSTL-2 Class
II
SSTL-3 Class
I
SSTL-3 Class
II
LVDS
-1X Speed Grade
Min
Max
1.5
290
1.5
281
1.5
272
1.5
303
1.5
291
1.5
291
1.5
300
1.5
300
1.5
420
-2X Speed Grade
Min
Max
1.5
257
1.5
250
1.5
243
1.5
261
1.5
253
Units
MHz
MHz
MHz
MHz
MHz
1.5
253 MHz
1.5
260 MHz
1.5
260 MHz
1.5
350 MHz
Notes to Tables 17 and 18:
(1) All input clock specifications must be met. The PLL may not lock onto an incoming clock if the clock specifications
are not met, creating an erroneous clock within the device.
(2) The maximum lock time is 40 µs or 2000 input clock cycles, whichever occurs first.
(3) Before configuration, the PLL circuits are disable and powered down. During configuration, the PLLs are still
disabled. The PLLs begin to lock once the device is in the user mode. If the clock enable feature is used, lock begins
once the CLKLK_ENA pin goes high in user mode.
(4) The PLL VCO operating range is 200 MHz ð f_VCO ð 840 MHz for LVDS mode.
SignalTap
Embedded
Logic Analyzer
APEX 20K devices include device enhancements to support the SignalTap
embedded logic analyzer. By including this circuitry, the APEX 20K
device provides the ability to monitor design operation over a period of
time through the IEEE Std. 1149.1 (JTAG) circuitry; a designer can analyze
internal logic at speed without bringing internal signals to the I/O pins.
This feature is particularly important for advanced packages such as
FineLine BGA packages because adding a connection to a pin during the
debugging process can be difficult after a board is designed and
manufactured.
54
Altera Corporation