EP20K300EQC240-1 Datasheet, PDF (72/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Figure 40. Synchronous Bidirectional Pin External Timing
Dedicated
Clock
OE Register (1)
PRN
DQ
t_XZBIDIR
t_ZXBIDIR
CLRN
Output IOE Register
PRN
DQ
t_OUTCOBIDIR
Bidirectional Pin
CLRN IOE Register
Input Register (1)(2)
PRN
DQ
t_INSUBIDIR
t_INHBIDIR
CLRN
Notes to Figure 40:
(1) The output enable and input registers are LE registers in the LAB adjacent to a
bidirectional row pin. The output enable register is set with “Output Enable
Routing= Signal-Pin” option in the Quartus II software.
(2) The LAB adjacent input register is set with “Decrease Input Delay to Internal Cells=
Off”. This maintains a zero hold time for lab adjacent registers while giving a fast,
position independent setup time. A faster setup time with zero hold time is possible
by setting “Decrease Input Delay to Internal Cells= ON” and moving the input
register farther away from the bidirectional pin. The exact position where zero hold
occurs with the minimum setup time, varies with device density and speed grade.
Table 31 describes the f_MAX timing parameters shown in Figure 36 on
page 68.
Table 31. APEX 20K f_MAX Timing Parameters (Part 1 of 2)
Symbol
t_SU
t_H
t_CO
t_LUT
t_ESBRC
t_ESBWC
t_ESBWESU
t_ESBDATASU
t_ESBDATAH
t_ESBADDRSU
t_ESBDATACO1
Parameter
LE register setup time before clock
LE register hold time after clock
LE register clock-to-output delay
LUT delay for data-in
ESB Asynchronous read cycle time
ESB Asynchronous write cycle time
ESB WE setup time before clock when using input register
ESB data setup time before clock when using input register
ESB data hold time after clock when using input register
ESB address setup time before clock when using input registers
ESB clock-to-output delay when using output registers
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