EP20K300EQC240-1 Datasheet, PDF (112/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Table 108. EP20K1500E External Bidirectional Timing Parameters
Symbol
t_{I N S U B I D I R}
t_{I N H B I D I R}
t_{O U T C O B I D I R}
t_{X Z B I D I R}
t_{Z X B I D I R}
t_{I N S U B I D I R P L L}
t_{I N H B I D I R P L L}
t_{O U T C O B I D I R P L L}
t_{X Z B I D I R P L L}
t_{Z X B I D I R P L L}
-1 Speed Grade
Min
Max
3.47
0.00
2.00
6.18
6.91
6.91
3.05
0.00
0.50
2.67
3.41
3.41
-2 Speed Grade
Min
Max
3.68
0.00
2.00
6.81
7.62
7.62
3.26
0.00
0.50
2.99
3.80
3.80
-3 Speed Grade
Unit
Min
Max
3.99
ns
0.00
ns
2.00
7.36
ns
8.38
ns
8.38
ns
ns
ns
ns
ns
ns
Tables 109 and 110 show selectable I/O standard input and output
delays for APEX 20KE devices. If you select an I/O standard input or
output delay other than LVCMOS, add or subtract the selected speed
grade to or from the LVCMOS value.
Table 109. Selectable I/O Standard Input Delays
Symbol
LVCMOS
LVTTL
2.5 V
1.8 V
PCI
GTL+
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
LVDS
CTT
AGP
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
Min
0.00
0.00
0.00
–0.11
0.01
–0.24
–0.32
–0.08
–0.17
–0.16
–0.12
0.00
0.00
0.00
0.00
0.04
0.03
0.09
–0.23
–0.21
0.03
–0.06
–0.05
–0.12
0.00
0.00
0.00
ns
0.00
ns
0.05
ns
0.04
ns
0.10
ns
–0.19
ns
–0.47
ns
–0.23
ns
–0.32
ns
–0.31
ns
–0.12
ns
0.00
ns
0.00
ns
112
Altera Corporation