EP20K300EQC240-1 Datasheet, PDF (29/117 Pages) Altera Corporation – Programmable Logic Device Family

Figure 16. APEX 20K Parallel Expanders
APEX 20K Programmable Logic Device Family Data Sheet
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Previous
Macrocell
Product-
Term
Select
Matrix
Parallel
Expander Switch
Macrocell
Product-
Term Logic
Product-
Term
Select
Matrix
Parallel
Expander Switch
Macrocell
Product-
Term Logic
32 Signals from
Local Interconnect
Embedded
System Block
To Next
Macrocell
The ESB can implement various types of memory blocks, including
dual-port RAM, ROM, FIFO, and CAM blocks. The ESB includes input
and output registers; the input registers synchronize writes, and the
output registers can pipeline designs to improve system performance. The
ESB offers a dual-port mode, which supports simultaneous reads and
writes at two different clock frequencies. Figure 17 shows the ESB block
diagram.
Figure 17. ESB Block Diagram
wraddress[]
data[]
wren
inclock
inclocken
inaclr
rdaddress[]
q[]
rden
outclock
outclocken
outaclr
Altera Corporation
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