EP20K300EQC240-1 Datasheet, PDF (32/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Read/Write Clock Mode
The read/write clock mode contains two clocks. One clock controls all
registers associated with writing: data input, WE, and write address. The
other clock controls all registers associated with reading: read enable
(RE), read address, and data output. The ESB also supports clock enable
and asynchronous clear signals; these signals also control the read and
write registers independently. Read/write clock mode is commonly used
for applications where reads and writes occur at different system
frequencies. Figure 20 shows the ESB in read/write clock mode.
Figure 20. ESB in Read/Write Clock Mode
Dedicated Inputs &
Global Signals
Dedicated Clocks
Note (1)
data[ ]
2 or 4 4
(2)
DQ
ENA
rdaddress[ ]
DQ
ENA
wraddress[ ]
rden
DQ
ENA
wren
outclocken
DQ
ENA
inclocken
inclock
outclock
DQ
ENA
Write
Pulse
Generator
RAM/ROM
128 × 16
256 × 8
Data In
512 × 4
1,024 × 2
2,048 × 1
Data Out
Read Address
DQ
ENA
Write Address
Read Enable
Write Enable
To MegaLAB,
FastTrack &
Local
Interconnect
Notes to Figure 20:
(1) All registers can be cleared asynchronously by ESB local interconnect signals, global signals, or the chip-wide reset.
(2) APEX 20KE devices have four dedicated clocks.
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Altera Corporation