1GB-AUTO-AS4C64M16D3 Datasheet, PDF(81/86 Page) Alliance Semiconductor Corporation – Supports JEDEC clock jitter specification

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1GB-AUTO-AS4C64M16D3 Datasheet, PDF (81/86 Pages) Alliance Semiconductor Corporation – Supports JEDEC clock jitter specification

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1Gb Auto-AS4C64M16D3

Figure 72. Asynchronous ODT Timings on DDR3 SDRAM with fast ODT transition

T10 T11

T12 T13 T14 T15 T16 T17

CK#

CKE

ODT

RTT

tIH

tIS

tAONPD(min)

tAONPD(max)

RTT

tIH

tIS

tAOFPD(min)

tAOFPD(max)

TRANSITIONING DATA

Don't Care

Figure 73. Synchronous to asynchronous transition during Precharge Power Down

(with DLL frozen) entry (AL = 0; CWL = 5; tANPD = WL - 1 = 4)

T10

T11

T12

CK#

COMMAND

NOP

CKE

Last sync.

ODT

RTT

Sync. or

async. ODT

RTT

First async.

ODT

RTT

tANPD

PD entry transition period

tCPDED(min)

tCPDED

ODTLoff

tAOF(min)

tAOF(max)

tAOFPD(max)

ODTLoff + tAOF(min)

tAOFPD(min)

ODTLoff + tAOF(max)

RTT

PD entry transition period

tAOFPD(min)

tAOFPD(max)

TRANSITIONING DATA

Don't Care

Confidential

--81/86

Rev.1.0 June 2015

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