1GB-AUTO-AS4C64M16D3 Datasheet, PDF (13/86 Pages) Alliance Semiconductor Corporation – Supports JEDEC clock jitter specification

1Gb Auto-AS4C64M16D3
The MRS command to Non-MRS command delay, tMOD, is require for the DRAM to update the features except
DLL reset, and is the minimum time required from an MRS command to a non-MRS command excluding NOP and
DES shown in Figure of tMOD timing.
Figure 7. tMOD timing
T0
T1
CK#
CK
T2
Ta0
Ta1
Ta2
Ta3
Ta4
Tb0
Tb1
Tb2
COMMAND
VALID
VALID
VALID
MRS
NOP/DES
NOP/DES
NOP/DES
NOP/DES
NOP/DES
VALID
VALID
ADDRESS
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
CKE
Settings
Old Settings
ODT
ODT
RTT_Nom ENABLED prior and/or after MRS command
VALID
VALID
ODTLoff + 1
RTT_Nom DISABLED prior and after MRS command
VALID
VALID
VALID
VALID
VALID
Updating Settings
t_MOD
VALID
VALID
VALID
VALID
New Settings
VALID
VALID
VALID
TIME BREAK
Don't Care
The mode register contents can be changed using the same command and timing requirements during normal
operation as long as the DRAM is in idle state, i.e., all banks are in the precharged state with tRP satisfied, all data
bursts are completed and CKE is high prior to writing into the mode register. The mode registers are divided into
various fields depending on the functionality and/or modes.
Confidential
--13/86
Rev.1.0 June 2015