1GB-AUTO-AS4C64M16D3 Datasheet, PDF (15/86 Pages) Alliance Semiconductor Corporation – Supports JEDEC clock jitter specification

1Gb Auto-AS4C64M16D3
- Burst Length, Type, and Order
Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected
via bit A3 as shown in the MR0 Definition as above figure. The ordering of access within a burst is determined by
the burst length, burst type, and the starting column address. The burst length is defined by bits A0-A1. Burst
lengths options include fix BC4, fixed BL8, and on the fly which allow BC4 or BL8 to be selected coincident with
the registration of a Read or Write command via A12/BC#
Table 6. Burst Type and Burst Order
Burst Length
Read
Write
Starting Column
Address
A2 A1 A0
000
Sequential
A3=0
0, 1, 2, 3, T, T, T, T
Interleave
A3=1
0, 1, 2, 3, T, T, T, T
Note
4
Chop
Read
0 0 1 1, 2, 3, 0, T, T, T, T 1, 0, 3, 2, T, T, T, T
0 1 0 2, 3, 0, 1, T, T, T, T 2, 3, 0, 1, T, T, T, T
0
1
1
0
1
0
3, 0, 1, 2, T, T, T, T 3, 2, 1, 0, T, T, T, T
4, 5, 6, 7, T, T, T, T 4, 5, 6, 7, T, T, T, T
1, 2, 3
1 0 1 5, 6, 7, 4, T, T, T, T 5, 4, 7, 6, T, T, T, T
1 1 0 6, 7, 4, 5, T, T, T, T 6, 7, 4, 5, T, T, T, T
1 1 1 7, 4, 5, 6, T, T, T, T 7, 6, 5, 4, T, T, T, T
Write
0
1
V
V
V
V
0, 1, 2, 3, X, X, X, X
4, 5, 6, 7, X, X, X, X
0, 1, 2, 3, X, X, X, X
4, 5, 6, 7, X, X, X, X
1, 2, 4, 5
0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7
0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6
0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5
8
Read
0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4
1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3
2
1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2
1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1
1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0
Write
V V V 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 2, 4
Note 1: In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles earlier than
for the BL8 mode. This means that the starting point for tWR and tWTR will be pulled in by two clocks. In case of burst
length being selected on-the-fly via A12/BC#, the internal write operation starts at the same point in time like a burst of
8 write operation. This means that during on-the-fly control, the starting point for tWR and tWTR will not be pulled in by
two clocks.
Note 2: 0~7 bit number is value of CA[2:0] that causes this bit to be the first read during a burst.
Note 3: T: Output driver for data and strobes are in high impedance.
Note 4: V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins.
Note 5: X: Don’t Care.
- CAS Latency
The CAS Latency is defined by MR0 (bit A2, A4~A6) as shown in the MR0 Definition figure. CAS Latency is the
delay, in clock cycles, between the internal Read command and the availability of the first bit of output data.
DDR3 SDRAM does not support any half clock latencies. The overall Read Latency (RL) is defined as Additive
Latency (AL) + CAS Latency (CL); RL = AL + CL.
- Test Mode
The normal operating mode is selected by MR0 (bit7=0) and all other bits set to the desired values shown in the
MR0 definition figure. Programming bit A7 to a ‘1’ places the DDR3 SDRAM into a test mode that is only used by
the DRAM manufacturer and should not be used. No operations or functionality is guaranteed if A7=1.
- DLL Reset
The DLL Reset bit is self-clearing, meaning it returns back to the value of ‘0’ after the DLL reset function has been
issued. Once the DLL is enabled, a subsequent DLL Reset should be applied. Anytime the DLL reset function is
used, tDLLK must be met before any functions that require the DLL can be used (i.e. Read commands or ODT
synchronous operations.)
Confidential
--15/86
Rev.1.0 June 2015