1GB-AUTO-AS4C64M16D3 Datasheet, PDF (19/86 Pages) Alliance Semiconductor Corporation – Supports JEDEC clock jitter specification

1Gb Auto-AS4C64M16D3
- Partial Array Self-Refresh (PASR)
Optional in DDR3 SDRAM: Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to
determine if DDR3 SDRAM devices support the following options or requirements referred to in this material.
If PASR (Partial Array Self-Refresh) is enabled, data located in areas of the array beyond the specified address
range will be lost if Self-Refresh is entered. Data integrity will be maintained if tREFI conditions are met and no
Self-Refresh command is issued.
- CAS Write Latency (CWL)
The CAS Write Latency is defined by MR2 (bits A3-A5) shown in MR2. CAS Write Latency is the delay, in clock
cycles, between the internal Write command and the availability of the first bit of input data. DDR3 DRAM does
not support any half clock latencies. The overall Write Latency (WL) is defined as Additive Latency (AL) + CAS
Write Latency (CWL); WL=AL+CWL.
For more information on the supported CWL and AL settings based on the operating clock frequency, refer to
“Standard Speed Bins”. For detailed Write operation refer to “WRITE Operation”.
- Auto Self-Refresh (ASR) and Self-Refresh Temperature (SRT)
DDR3 SDRAM must support Self-Refresh operation at all supported temperatures. Applications requiring Self-
Refresh operation in the Extended Temperature Range must use the ASR function or program the SRT bit
appropriately.
Optional in DDR3 SDRAM: Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to
determine if DDR3 SDRAM devices support the following options or requirements referred to in this material.
For more details refer to “Extended Temperature Usage”. DDR3 SDRAMs must support Self-Refresh operation
at all supported temperatures. Applications requiring Self-Refresh operation in the Extended Temperature
Range must use the optional ASR function or program the SRT bit appropriately.
- Dynamic ODT (Rtt_WR)
DDR3 SDRAM introduces a new feature “Dynamic ODT”. In certain application cases and to further enhance
signal integrity on the data bus, it is desirable that the termination strength of the DDR3 SDRAM can be
changed without issuing an MRS command. MR2 Register locations A9 and A10 configure the Dynamic ODT
settings.
DDR3 SDRAM introduces a new feature “Dynamic ODT”. In certain application cases and to further enhance
signal integrity on the data bus, it is desirable that the termination strength of the DDR3 SDRAM can be
changed without issuing an MRS command. MR2 Register locations A9 and A10 configure the Dynamic ODT
settings. In Write leveling mode, only RTT_Nom is available. For details on Dynamic ODT operation, refer to
“Dynamic ODT”.
Confidential
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Rev.1.0 June 2015