1GB-AUTO-AS4C64M16D3 Datasheet, PDF (27/86 Pages) Alliance Semiconductor Corporation – Supports JEDEC clock jitter specification

1Gb Auto-AS4C64M16D3
t_MPRR
t_RRD
t_FAW
t_IS(base)
t_IS(base)
t_IH(base)
t_IPW
t_ZQinit
t_ZQoper
t_ZQCS
t_XPR
t_XS
t_XSDLL
t_CKESR
t_CKSRE
t_CKSRX
t_XP
t_XPDLL
t_CKE
t_CPDED
t_PD
t_ACTPDEN
t_PRPDEN
t_RDPDEN
t_WRPDEN
t_WRAPDEN
Multi-Purpose Register Recovery Time
ACTIVE to ACTIVE command period
Four activate window
1
max (4tCK,
7.5ns)
40
Command and Address setup time to CK, ^AC175
45
CK# referenced to Vih(ac) / Vil(ac) levels _AC150
170
Command and Address hold time from CK,
CK# referenced to Vih(dc) / Vil(dc) levels
DC100
120
Control and Address Input pulse width for each input
560
Power-up and RESET calibration time
512
Normal operation Full calibration time
256
Normal operation Short calibration time
64
Exit Reset from CKE HIGH to a valid command
max (5tCK,
tRFC(min) +
10ns)
Exit Self Refresh to commands not
requiring a locked DLL
max (5tCK,
tRFC(min) +
10ns)
Exit Self Refresh to commands requiring a
locked DLL
tDLLK (min)
Minimum CKE low width for Self Refresh
entry to exit timing
tCKE (min) +
1tCK
Valid Clock Requirement after Self Refresh Entry (SRE) max(5t_CK,
or Power-Down Entry (PDE)
10 ns)
Valid Clock Requirement before Self Refresh Exit (SRX) max (5t_CK,
or Power-Down Exit (PDX) or Reset Exit
10 ns)
Exit Power Down with DLL on to any valid command;
Exit Precharge Power Down with DLL frozen to
commands not requiring a locked DLL
max (3tCK,
6 ns)
Exit Precharge Power Down with DLL
frozen to commands requiring a lockedDLL
max (10tCK,
24 ns)
CKE minimum pulse width
max (3tCK,
5 ns)
Command pass disable delay
2
Power Down Entry to Exit Timing
Timing of ACT command to Power Down
entry
Timing of PRE or PREA command to
Power Down entry
Timing of RD/RDA command to Power
Down entry
Timing of WR command to Power Down
entry (BL8OTF, BL8MRS, BC4OTF)
tCKE (min)
1
1
RL + 4 + 1
WL + 4 +
(tWR / tCK)
Timing of WRA command to Power
Down entry (BL8OTF, BL8MRS,BC4OTF)
WL + 4 +
WR + 1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
9 * tREFI
-
-
-
-
-
t_WRPDEN
Timing of WR command to Power Down entry
(BC4MRS)
WL + 2 +
(tWR / tCK)
-
t_WRAPDEN
t_REFPDEN
t_MRSPDEN
ODTLon
ODTLoff
ODTH4
ODTH8
t_AONPD
t_AOFPD
t_AON
Timing of WRA command to Power Down entry
(BC4MRS)
Timing of REF command to Power Down entry
Timing of MRS command to Power Down entry
ODT turn on Latency
ODT turn off Latency
ODT high time without write command or
with write command and BC4
ODT high time with Write command and BL8
Asynchronous RTT turn-on delay (Power- Down with
DLL frozen)
Asynchronous RTT turn-off delay (Power-
Down with DLL frozen)
RTT turn-on
WL + 2 +
WR + 1
-
1
-
tMOD (min)
-
WL - 2 = CWL + AL - 2
WL - 2 = CWL + AL - 2
4
-
6
-
2
8.5
2
8.5
-225
225
Confidential
--27/86
tCK
22
tCK
ns
ps
16
ps
16,27
ps
16
ps
28
tCK
tCK
tCK
23
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
2
tCK
tCK
15
tCK
20
tCK
20
tCK
tCK
9
tCK
10
tCK
9
tCK
10
tCK
20, 21
tCK
tCK
tCK
ns
ns
ps
7
Rev.1.0 June 2015