1GB-AUTO-AS4C64M16D3 Datasheet, PDF (73/86 Pages) Alliance Semiconductor Corporation – Supports JEDEC clock jitter specification

1Gb Auto-AS4C64M16D3
Figure 55. Active Power-Down Entry and Exit Timing Diagram
T0
T1
T2
Ta0
Ta1
Tb0
Tb1
Tc0
CK#
CK
COMMAND
CKE
ADDRESS
VALID
t_IH
NOP
t_IS
NOP
t_PD
NOP
NOP
t_IH
t_IS
t_CKE
NOP
VALID
VALID
t_CPDED
t_XP
Enter
Power-Down Mode
Exit
Power-Down Mode
NOTE:
TIME BREAK
VALID command at T0 is ACT, NOP, DES or PRE with still one bank remaining
open after completion of the precharge command.
VALID
VALID
VALID
Don't Care
Figure 56. Power-Down Entry after Read and Read with Auto Precharge
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Ta8
Tb0
Tb1
CK#
CK
COMMAND
CKE
RD or
RDA
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
t_IS
t_CPDED
NOP
VALID
VALID
ADDRESS
VALID
DQS, DQS#
DQ BL8
DQ BC4
RL = AL + CL
VALID
t_PD
Din
Din
Din
Din
Din
Din
Din
Din
b
b+1
b+2
b+3
b+4
b+5
b+6
b+7
t_RDPDEN
Din
Din
Din
Din
b
b+1
b+2
b+3
Power - Down Entry
TIME BREAK
TRANSITIONING DATA
Don't Care
Confidential
--73/86
Rev.1.0 June 2015