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1GB-AUTO-AS4C64M16D3 Datasheet, PDF (69/86 Pages) Alliance Semiconductor Corporation – Supports JEDEC clock jitter specification
1Gb Auto-AS4C64M16D3
Figure 43. WRITE(BC4) to READ (BC4) operation
T0
T1
T2
T3
T4
T5
CK#
CK
Notes 3
COMMAND
WRITE
NOP
NOP
NOP
NOP
NOP
Notes 4
ADDRESS
Bank,
Col n
DQS, DQS#
tWPRE
T6
T7
NOP
NOP
tWPST
T8
T9
Tn
NOP
NOP
t Notes 5
WTR
READ
Notes 2
DQ
WL = 5
Din
Din
Din
Din
n
n+1
n+2
n+3
NOTES:
1. BC4, WL = 5, RL = 5.
2. DIN n = data-in from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0[A1:0 = 10] during WRITE command at T0 and READ command at Tn.
5. tWTR controls the write to read delay to the same device and starts with the first rising clock edge after the last write data shown at T7.
TIME BREAK
TRANSITIONING DATA
RL = 5
Don't Care
Figure 44. WRITE(BC4) to Precharge Operation
T0
T1
T2
T3
T4
T5
CK#
CK
Notes 3
COMMAND
WRITE
NOP
NOP
NOP
NOP
NOP
Notes 4
ADDRESS
Bank,
Col n
DQS, DQS#
tWPRE
T6
T7
NOP
NOP
tWPST
T8
T9
Tn
NOP
NOP
t Notes 5
WR
PRE
Notes 2
DQ
WL = 5
Din
Din
Din
Din
n
n+1
n+2
n+3
NOTES:
1. BC4, WL = 5, RL = 5.
2. DIN n = data-in from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0[A1:0 = 10] during WRITE command at T0.
5. The write recovery time (tWR) referenced from the first rising clock edge after the last write data shown at T7.
tWR specifies the last burst write cycle until the precharge command can be issued to the same bank .
TIME BREAK
TRANSITIONING DATA
Don't Care
Figure 45. WRITE(BC4) OTF to Precharge operation
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
Notes 3
COMMAND
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Notes 4
ADDRESS
Bank
Col n
DQS, DQS#
Notes 2
DQ
WL = 5
tWPRE
4 Clocks
tWPST
Din
Din
Din
Din
n
n+1
n+2
n+3
NOTES:
1. BC4 OTF, WL = 5 (CWL = 5, AL = 0)
2. DIN n (or b) = data-in from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 OTF setting activated by MR0[A1:0 = 01] and A12 = 0 during WRITE command at T0.
5. The write recovery time (tWR) starts at the rising clock edge T9 (4 clocks from T5).
T9
T10
T11
Ta0
Ta1
Ta2
NOP
NOP
NOP
t Notes 5
WR
PRE
VALID
NOP
NOP
TIME BREAK
TRANSITIONING DATA
Don't Care
Confidential
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Rev.1.0 June 2015