1GB-AUTO-AS4C64M16D3 Datasheet, PDF(25/86 Page) Alliance Semiconductor Corporation – Supports JEDEC clock jitter specification

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1GB-AUTO-AS4C64M16D3 Datasheet, PDF (25/86 Pages) Alliance Semiconductor Corporation – Supports JEDEC clock jitter specification

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1Gb Auto-AS4C64M16D3

Burst Refresh Current

CKE: High; External clock: On; BL: 8*1; AL: 0; CS#: High between tREF;

Command, Address, Bank Address Inputs: partially toggling; Data IO: MID- IDD5B

114

LEVEL;DM:stable at 0; Bank Activity: REF command every tRFC; Output

Buffer and RTT: Enabled in Mode Registers*2; ODT Signal: stable at 0.

Self Refresh Current:

Auto Self-Refresh (ASR): Disabled*4; Self-Refresh Temperature Range

(SRT): Normal*5; CKE: Low; External clock: Off; CK and CK#: LOW; BL: 8*1;

AL: 0; CS#, Command, Address, Bank Address, Data IO: MID-

IDD6

LEVEL;DM:stable at 0; Bank Activity: Self-Refresh operation; Output Buffer

and RTT: Enabled in Mode Registers*2; ODT Signal: MID-LEVEL

Operating Bank Interleave Read Current

CKE: High; External clock: On; BL: 8*1, 7; AL: CL-1; CS#: High between ACT

and RDA; Command, Address, Bank Address Inputs: partially toggling;

IDD7

240

DM:stable at 0; Output Buffer and RTT: Enabled in Mode Registers*2; ODT

Signal: stable at 0.

RESET Low Current

RESET: LOW; External clock: Off; CK and CK#: LOW; CKE: FLOATING;

CS#, Command, Address,

Bank Address, Data IO: FLOATING; ODT Signal: FLOATING

IDD8

RESET Low current reading is valid once power is stable and RESET has

been LOW for at least 1ms.

NOTE 1: Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B

NOTE 2: Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B;

RTT_Wr enable: set MR2 A[10,9] = 10B

NOTE 3: Pecharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit

NOTE 4: Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature

NOTE 5: Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range

NOTE 6: Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are

supported by DDR3 SDRAM device

NOTE 7: Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B

Confidential

--25/86

Rev.1.0 June 2015

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