1GB-AUTO-AS4C64M16D3 Datasheet, PDF (20/86 Pages) Alliance Semiconductor Corporation – Supports JEDEC clock jitter specification

1Gb Auto-AS4C64M16D3
l Mode Register MR3
The Mode Register MR3 controls Multi-purpose registers. The Mode Register 3 is written by asserting low on
CS#, RAS#, CAS#, WE#, high on BA1 and BA0, and low on BA2 while controlling the states of address pins
according to the table below
Table 9. Extended Mode Register EMR (3) Bitmap
BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field
0^*1
1
1
0^*1
MPR MPR Loc Mode Register (3)
BA1 BA0 MRS mode
00
MR0
01
MR1
10
MR2
11
MR3
A2
MPR
0
Normal operation ^*3
1
Dataflow from MPR
A1 A0 MPR location
0 0 Predefined pattern ^*2
01
RFU
10
RFU
11
RFU
Note 1: BA2, A3 - A12 are RFU and must be programmed to 0 during MRS.
Note 2: The predefined pattern will be used for read synchronization.
Note 3: When MPR control is set for normal operation (MR3 A[2] = 0) then MR3 A[1:0] will be ignored.
Confidential
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Rev.1.0 June 2015