1GB-AUTO-AS4C64M16D3 Datasheet, PDF (78/86 Pages) Alliance Semiconductor Corporation – Supports JEDEC clock jitter specification

1Gb Auto-AS4C64M16D3
Figure 65. Synchronous ODT Timing Example
(AL = 3; CWL = 5; ODTLon = AL + CWL - 2 = 6; ODTLoff = AL + CWL - 2 = 6)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK#
CK
CKE
ODT
DRAM_RTT
AL = 3
ODTH4, min
ODTLon = CWL + AL - 2
AL = 3
tAON(min)
RTT_NOM
tAON(max)
ODTLoff = CWL + AL - 2
T12
T13
T14
T15
CWL - 2
tAOF(min)
tAOF(max)
TRANSITIONING DATA
Don't Care
Figure 66. Synchronous ODT example with BL = 4, WL = 7
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK#
CK
CKE
ODTH4
ODTH4min
ODTH4
COMMAND
NOP
NOP
NOP
NOP
NOP
NOP
NOP
WRS4
NOP
NOP
NOP
NOP
T12
T13
NOP
NOP
T14
T15
T16
T17
NOP
NOP
NOP
NOP
ODT
DRAM_RTT
ODTLon = WL - 2
tAON(min)
ODTLoff = WL - 2
ODTLon = WL - 2
tAON(max)
RTT_NOM
tAOF(min)
tAON(max)
ODTLoff = WL - 2
tAOF(max)
tAON(min)
tAOF(min)
tAOF(max)
TRANSITIONING DATA
Don't Care
Figure 67. Dynamic ODT Behavior with ODT being asseted before and after the write
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
CK#
CK
COMMAND
NOP
NOP
NOP
NOP
WRS4
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ADDRESS
ODT
RTT
DQS, DQS#
DQ
ODTH4
VALID
ODTH4
ODTLon
tAON(min)
tAON(max)
ODTLcwn4
RTT_NOM
ODTLcnw
tADC(min)
tADC(max)
WL
RTT_WR
tADC(min)
tADC(max)
Din
Din
Din
Din
n
n+1
n+2
n+3
NOTES:
Example for BC4 (via MRS or OTF), AL = 0, CWL = 5. ODTH4 applies to first registering ODT high and to the registration of the Write command.
In this example, ODTH4 would be satisfied if ODT went low at T8 (4 clocks after the Write command).
ODTLoff
RTT_NOM
tAOF(min)
tAOF(max)
TRANSITIONING DATA
Don't Care
Confidential
--78/86
Rev.1.0 June 2015