1GB-AUTO-AS4C64M16D3 Datasheet, PDF (34/86 Pages) Alliance Semiconductor Corporation – Supports JEDEC clock jitter specification

1Gb Auto-AS4C64M16D3
l DLL “off” to DLL “on” Procedure
To switch from DLL “off” to DLL “on” (with requires frequency change) during Self-Refresh:
1. Starting from Idle state (all banks pre-charged, all timings fulfilled and DRAMs On-die Termination resistors
(RTT) must be in high impedance state before Self-Refresh mode is entered).
2. Enter Self Refresh Mode, wait until tCKSRE satisfied.
3. Change frequency, in guidance with “Input clock frequency change” section.
4. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs.
5. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until tDLLK timing
from subsequent DLL Reset command is satisfied. In addition, if any ODT features were enabled in the mode
registers when Self Refresh mode was entered, the ODT signal must continuously be registered LOW until
tDLLK timings from subsequent DLL Reset command is satisfied. If both ODT features are disabled in the
mode registers when Self Refresh mode was entered, ODT signal can be registered LOW or HIGH.
6. Wait tXS, then set MR1 Bit A0 to “0” to enable the DLL.
7. Wait tMRD, then set MR0 Bit A8 to “1” to start DLL Reset.
8. Wait tMRD, then set Mode registers with appropriate values (especially an update of CL, CWL, and WR may
be necessary. After tMOD satisfied from any proceeding MRS command, a ZQCL command may also be
issued during or after tDLLK).
9. Wait for tMOD, then DRAM is ready for next command (remember to wait tDLLK after DLL Reset before
applying command requiring a locked DLL!). In addition, wait also for tZQoper in case a ZQCL command was
issued.
Figure 11. DLL Switch Sequence from DLL-off to DLL on
T0
Ta0
Ta1
Tb0
Tc0
Tc1
Td0
Te0
Tf1
Tg0
Th0
CK#
CK
CKE
COMMAND
NOP
Notes 2
SRE
NOP
Notes 1 ODTLoff + 1 * tCK
t_CKSRE
Notes 3
t_CKESR
Notes 5
Notes 6
t_DLLK
Notes 7
Notes 8
VALID
Notes 9
SRX
MRS
MRS
MRS
VALID
Notes 4
t_CKSRX
t_XS
t_MRD
t_MRD
ODT
ODT: Static LOW in case RTT_Nom and RTT_WR is enabled, otherwise static Low or High
NOTES:
1. Starting with Idle State
2. Enter SR
3. Change Frequency
4. Clock must be stable tCKSRX
5. Exit SR
6. Set DLL on by MR1 A0 = 0
7. Start DLL Reset by MR0 A8=1
8. Update Mode registers
9. Any valid command
TIME BREAK
Don't Care
Confidential
--34/86
Rev.1.0 June 2015