AK4636 Datasheet, PDF (92/105 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK/Video-AMP

[AK4636]
3. When the external clock (MCKI pin) is used in PLL Slave mode.
Power Supply
PDN pin
PMVCM bit
(Addr:00H, D6)
PMPLL bit
(Addr:01H, D0)
MCKI pin
MCKO pin
BICK pin
FCK pin
(1)
(2) (3)
(4)
(5)
Input
20msec(max)
(6)
(7)
(8)
Output
Input
Example:
Audio I/F Format: MSB justified
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 12MHz
MCKO : Enable
Sampling Frequency:48kHz
(1) Power Supply & PDN pin = “L” Æ “H”
(2)Addr:04H, Data:68H
Addr:05H, Data:23H
(3)Addr:00H, Data:40H
(4)Addr:01H, Data:03H
MCKO output start
BICK and FCK input start
Figure 72. Clock Set Up Sequence (3)
<Example>
(1) After Power Up: PDN pin “L” → “H”
“L” time (1) of 150ns or more is needed to reset the AK4636.
(2) DIF1-0, PLL3-0, FS3-0, BCKO1-0, MSBS, BCKP and M/S bits must be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” → “1”
VCOM should first be powered up before the other block operates.
(4) PLL Power Up: PMPLL bit “0” → “1”
(5) PLL lock time is 20ms(max) after the PMPLL bit changes from “0” to “1” and PLL reference clock (MCKI pin)
is supplied.
(6) Normal clock is output from the MCKO pin after PLL is locked.
(7) The invalid frequency is output from the MCKO pin during this period.
(8) BICK and FCK clocks should be synchronized with MCKO clock.
MS1012-E-01
- 92 -
2010/08