AK4636 Datasheet, PDF (65/105 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK/Video-AMP

[AK4636]
■ Speaker Output
AK4636 has a Mono Class-D Speaker-Amp. Power supply for Speaker-Amp can be set from 2.6V up to 3.6V.
The output signal from DAC is input to the Speaker-amp. This Speaker-amp is a mono output controlled by BTL and the
gain of Speaker-Amp is set by SPKG1-0 bits. The output voltage is depend on SPKG1-0 bits.
DAC
SPK-amp
Output Level
SPKG1-0 bits Gain
OUT (R=8Ω)
00
10.6dB 3.17Vpp 157mW (default)
-4.1dBFS 0.94Vpp
01
10
12.6dB 4.00Vpp 250mW
14.6dB 5.03Vpp 395mW
11
N/A
N/A
N/A
Note 41. The setting of SPKG1-0 bits = “01” is recommended when 8Ω dynamic speaker is connected.
The SPK-Amp Power is 250mW at 8Ω Load Resistance and 4.0Vpp output level.
Table 55. SPK- Amp Gain
< Speaker-Amp Control Sequence >
Speaker-Amp is powered-up/down by PMSPK bit. When PMSPK bit is “0”, both SPP and SPN pins are in Hi-Z state.
When PMSPK bit is “1” and SPPSN bit is “0”, the Speaker-Amp enters power-save mode. In this mode, the SPP pin is
placed in Hi-Z state and the SPN pin outputs SVDD/2 voltage.
When the PMSPK bit is “1” after the PDN pin is changed from “L” to “H”, the SPP and SPN pins are powered-up in
power-save-mode. In this mode, the SPP pin is placed in a Hi-Z state and the SPN pin goes to SVDD/2 voltage and pop
noise can be reduced. When the AK4646 is powered-down, pop noise can be also reduced by first entering
power-save-mode.
PMSPKbit
SPPSNb i t
SPPpin
Hi-Z
Hi-Z
SPNpin _Hi-Z ^SVDD/2
SVDD/2
Hi-Z
>t1(Note)
>0
(Note)
SPPSN bit should be set to “1” at more than 1ms after PMSPK bit is set to “1”. When BEEP Input Amp and Speaker Amp
are powered-up at the same time, SPPSN bit should be set to “1” after BEEP Input become stable. When the resistance
and capacitance of BEEP pin are R=33kΩ and C=0.1μF, 16.5ms(=5τ) is required for BEEP Input to become stable.
Figure 53. Power-up/Power-down Timing for Speaker-Amp
MS1012-E-01
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2010/08