AK4636 Datasheet, PDF (29/105 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK/Video-AMP

[AK4636]
When PLL2 bit is “0” (PLL reference clock input is FCK or BICK pin), the sampling frequency is selected by FS3-2
bits. (Table 6)
Mode
0
1
2
Others
FS3 bit FS2 bit
FS1 bit
FS0 bit
Sampling Frequency
Range
0
0
x
x
7.35kHz ≤ fs ≤ 12kHz (default)
0
1
x
x
12kHz < fs ≤ 24kHz
1
0
x
x
24kHz < fs ≤ 48kHz
Others
N/A
(x: Don’t care, N/A: Not available)
Table 6. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL bit = “1”
■ PLL Unlock State
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In this mode, after PMPLL bit = “0” Æ “1” until the PLL is locked, the BICK and FCK pins output “L” for a moment, and
invalid frequency clock is output from the MCKO pin at MCKO bit = “1”. If the MCKO bit is “0”, the MCKO pin outputs
“L”. (Table 7)
When sampling frequency is changed, BICK and FCK pins do not output irregular frequency clocks but go to “L” by
setting PMPLL bit to “0”.
PLL State
MCKO pin
MCKO bit = “0” MCKO bit = “1”
After that PMPLL bit “0” Æ “1” “L” Output
Invalid
BICK pin
“L” Output
FCK pin
“L” Output
PLL Unlock
“L” Output
Invalid
Invalid
Invalid
PLL Lock
“L” Output
256fs Output
See Table 9
1fs Output
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from the MCKO pin after PMPLL bit = “0” Æ “1” or sampling frequency is
changed. 256fs is output from the MCKO pin when PLL is locked again. ADC and DAC output invalid data when the
PLL is unlocked. For DAC, the output signal should be muted by writing “0” to DACA and DACS bits in Addr=02H.
PLL State
After that PMPLL bit “0” Æ “1”
MCKO pin
MCKO bit = “0” MCKO bit = “1”
“L” Output
Invalid
PLL Unlock
“L” Output
Invalid
PLL Lock
“L” Output
Output
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
MS1012-E-01
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2010/08