AK4636 Datasheet, PDF (28/105 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK/Video-AMP

[AK4636]
■ Master Mode/Slave Mode
The M/S bit selects either master or slave modes. M/S bit = “1” selects master mode and “0” selects slave mode. When the
AK4636 is power-down mode (PDN pin = “L”) and when exits reset state, the AK4636 is in slave mode. After exiting
reset state, the AK4636 changes to master mode by bringing M/S bit = “1”.
When the AK4636 is in master mode, FCK and BICK pins are a floating state until M/S bit becomes “1”. The FCK and
BICK pins of the AK4636 should be pulled-down or pulled-up by about 100kΩ resistor externally to avoid the floating
state.
M/S bit
Mode
0
Slave Mode
(default)
1
Master Mode
Table 3. Select Master/Salve Mod
■ PLL Mode
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the
PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 4. Ether when the AK4636 is supplied stable clocks after
PLL is powered-up (PMPLL bit = “0” → “1”) or when the sampling frequency changes, the PLL lock time is the same.
1) Setting of PLL Mode
PLL3 PLL2 PLL1 PLL0 PLL Reference
Input
Mode
bit bit bit bit Clock Input Pin Frequency
R and C of
VCOC pin
(Note 32)
R[Ω] C[F]
PLL Lock
Time
(max)
0
0
0
0
0
FCK pin
1fs
6.8k 220n 160ms
1
0
0
0
1
BICK pin
16fs
10k 4.7n
2ms
2
0
0
1
0
BICK pin
32fs
10k 4.7n
2ms
3
0
0
1
1
BICK pin
64fs
10k 4.7n
2ms
4
0
1
0
0
MCKI pin 11.2896MHz 10k 4.7n
10ms
6
0
1
1
0
MCKI pin
12MHz
10k 4.7n
10ms
7
0
1
1
1
MCKI pin
24MHz
10k 4.7n
10ms
12
1
1
0
0
MCKI pin
13.5MHz 10k 10n
10ms
13
1
1
0
1
MCKI pin
27MHz
10k 10n
10ms
Others
Others
N/A
Note 32. The tolerance of R is ±5%, the tolerance of C is ±30%
Table 4. Setting of PLL Mode (*fs: Sampling Frequency, N/A: Not available)
(default)
2) Setting of sampling frequency in PLL Mode.
When PLL2 bit is “1” (PLL reference clock input is the MCKI pin), the sampling frequency is selected by FS3-0 bits as
defined in Table 5.
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit Sampling Frequency
0
0
0
0
0
8kHz
(default)
1
0
0
0
1
12kHz
2
0
0
1
0
16kHz
3
0
0
1
1
24kHz
4
0
1
0
0
7.35kHz
5
0
1
0
1
11.025kHz
6
0
1
1
0
14.7kHz
7
0
1
1
1
22.05kHz
10
1
0
1
0
32kHz
11
1
0
1
1
48kHz
14
1
1
1
0
29.4kHz
15
1
1
1
1
44.1kHz
Others
Others
N/A
Table 5. Setting of Sampling Frequency at PLL2 bit = “1” and PMPLL bit = “1” (N/A: Not available)
MS1012-E-01
- 28 -
2010/08