AK4636 Datasheet, PDF (100/105 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK/Video-AMP

[AK4636]
■ Stop of Clock
Master clock can be stopped when ADC, DAC and Programmable Filter are not in operation.
1. PLL Master Mode
PMPLL bit
(Addr:01H, D0)
MCKO bit
(Addr:01H, D1)
External MCKI
"H" or "L"
Input
(1)
(2)
(3)
Example:
Audio I/F Format: MSB justified
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 12MHz
MCKO : Enable
Sampling Frequency:48kHz
(1) (2) Addr:01H, Data:08H
Stop an external MCKI
Figure 80. Clock Stopping Sequence (1)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop MCKO clock: MCKO bit = “1” → “0”
(3) Stop an external master clock
2. PLL Slave Mode (FCK, BICK pin)
PMPLL bit
(Addr:01H,D0)
External BICK
External FCK
(1)
(2)
Input
(2)
Input
Example
Audio I/F Format: DSP Mode BCKP = MSBS = “0”
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 48kH z
(1) Addr:01H, Data:00H
(2) Stop the external clocks
Figure 81. Clock Stopping Sequence (2)
<Example>
(1) Power down of the PLL: PMPLL bit = “1” → “0”
(2) Stop an external master clock
MS1012-E-01
- 100 -
2010/08