AK4636 Datasheet, PDF (58/105 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK/Video-AMP

[AK4636]
7. Example of ALC Operation
The following registers must not be changed during the ALC operation. These bits should be changed, after the ALC
operation is finished by ALC1 bit = ALC2 bit = “0” or PMPFIL bit = “0”. When ALC is restarted, after ALC1 bit and
ALC2 bit set to “0” or PMPFIL bit sets to “0”, the waiting time of zero crossing timeout is not needed.
LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, IREF7-0/OREF5-0, ZELM,
RFST1-0, LFST, NSCE, NSTHL3-0, NSTHH1-0, NSGAIN1-0, NSREF7-0 bits
Manual Mode
WR (ZTM1-0, WTM2-0)
WR (IREF7-0/OREF5-0)
WR (IVOL7-0/OVOL7-0)
*1
WR (RGAIN1, LMTH1,RFST1-0)
WR (LFST,LMAT1-0, RGAIN0, ZELMN, LMTH0)
WR (ALC1= “1”)
*2
ALC Operation
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 16ms@8kHz
Limiter and Recovery Step = 1
LFST = 1
Maximum Gain = +19.5dB
Limiter Detection Level = −4.1dBFS
ALC1 bit = “1”
(1) Addr=06H, Data=00H
(2) Addr=08H, Data=C5H
(3) Addr=09H, Data=C5H
(4) Addr=0BH, Data=28H
(5) Addr=07H, Data=A1H
Note. WR: Write
*1: The value of volume at starting should be the same or smaller than REF’s.
*2: When setting ALC1 bit or ALC2 bit to “0”, the operation is shifted to manual mode after passing the zero crossing
time set by ZTM1-0 bits.
Figure 47. Registers set-up sequence at the ALC operation
MS1012-E-01
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2010/08