AK4343 Datasheet, PDF (81/98 Pages) Asahi Kasei Microsystems – Stereo DAC with HP/RCV/SPK-AMP

ASAHI KASEI
[AK4343]
SYSTEM DESIGN
Figure 72 and Figure 73 shows the system connection diagram for the AK4343. An evaluation board [AKD4343] is
available which demonstrates the optimum layout, power supply arrangements and measurement results.
Headphone
Speaker
Power Supply ^10u
2.6 ∼ 3.6V
10 0.22u
10 0.22u
ZD2
ZD1
Dynamic SPK
R1, R2: Short
ZD1, ZD2: Open
Piezo SPK
R1, R2: ≥10Ω
ZD1, ZD2: Required
Line Out
Mono In
Line In
1u
0.1u
25 MUTET
DVSS 16
200
1u
26 ROUT
DVDD 15
200
1u
27 LOUT
BICK 14
28 MIN
AK4343EN
LRCK 13
DSP
29 RIN2
Top View
NC 12
30 LIN2
SDTI 11
31 LIN1
CDTI 10
32 RIN1
CCLK 9
µP
Cp
Analog Ground Digital Ground
Notes:
- AVSS, DVSS and HVSS of the AK4343 should be distributed separately from the ground of external
controllers.
- All digital input pins should not be left floating.
- When the AK4343 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC pin is not needed.
- When the AK4343 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of VCOC pin is shown in Table 5.
- When piezo speaker is used, 2.6 ∼ 5.25V power should be supplied to HVDD and 10Ω or more series resistors
should be connected to both SPP and SPN pins, respectively.
- When the AK4343 is used at master mode, LRCK and BICK pins are floating before M/S bit is changed to “1”.
Therefore, 100kΩ around pull-up resistor should be connected to LRCK and BICK pins of the AK4343.
Figure 72. Typical Connection Diagram (AIN3 bit = “0”, Line Input)
MS0478-E-01
- 81 -
2006/10