AK4343 Datasheet, PDF (30/98 Pages) Asahi Kasei Microsystems – Stereo DAC with HP/RCV/SPK-AMP

ASAHI KASEI
[AK4343]
„ EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
When PMPLL bit is “0”, the AK4343 becomes EXT mode. Master clock is input from MCKI pin, the internal PLL circuit
is not operated. This mode is compatible with I/F of the normal audio DAC. The clocks required to operate are MCKI
(256fs, 512fs or 1024fs), LRCK (fs) and BICK (≥32fs). The master clock (MCKI) should be synchronized with LRCK.
The phase between these clocks does not matter. The input frequency of MCKI is selected by FS1-0 bits (see Table 12).
Mode
0
1
2
3
FS3-2 bits
FS1 bit FS0 bit
MCKI Input
Frequency
Sampling Frequency
Range
Don’t care
0
0
256fs
7.35kHz ∼ 48kHz
Don’t care
0
1
1024fs
7.35kHz ∼ 13kHz
Don’t care
1
0
256fs
7.35kHz ∼ 48kHz
Don’t care
1
1
512fs
7.35kHz ∼ 26kHz
Table 12. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
Default
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output
through LOUT/ROUT pins at fs=8kHz is shown in Table 13.
MCKI
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
256fs
83dB
512fs
93dB
1024fs
93dB
Table 13. Relationship between MCKI and S/N of LOUT/ROUT pins
The external clocks (MCKI, BICK and LRCK) should always be present whenever the DAC is in operation (PMDAC bit
= “1”). If these clocks are not provided, the AK4343 may draw excess current and it is not possible to operate properly
because utilizes dynamic refreshed logic internally. If the external clocks are not present, the DAC should be in the
power-down mode (PMDAC bit = “0”).
AK4343
MCKO
MCKI
BICK
LRCK
SDTI
256fs, 512fs or 1024fs
DSP or µP
MCLK
≥ 32fs
BCLK
1fs
LRCK
SDTO
Figure 22. EXT Slave Mode
MS0478-E-01
- 30 -
2006/10