AK4343 Datasheet, PDF (60/98 Pages) Asahi Kasei Microsystems – Stereo DAC with HP/RCV/SPK-AMP

ASAHI KASEI
[AK4343]
„ Speaker Output
Power supply for Speaker-Amp (HVDD) is 2.6V to 5.25V.
Speaker Type
Dynamic Speaker
Piezo (Ceramic) Speaker
Load Resistance (min)
8Ω
50Ω
Load Capacitance (max)
30pF
3µF
Note 19. Load impedance is total impedance of series resistance (Rseries) and piezo speaker impedance at 1kHz in Figure
58. Load capacitance is capacitance of piezo speaker. When piezo speaker is used, 10Ω or more series resistors
should be connected at both SPP and SPN pins, respectively.
Table 52. Speaker Type and Power Supply Range
The DAC or LIN2/RIN2/LIN3/RIN3 signal is input to the Speaker-amp as [(L+R)/2]. The Speaker-amp is mono and BTL
output. The gain is set by SPKG1-0 bits. Output level depends on AVDD voltage and SPKG1-0 bits.
SPKG1-0 bits
00
01
10
11
Gain
ALC bit = “0”
ALC bit = “1”
+4.43dB
+6.43dB
+6.43dB
+8.43dB
+10.65dB
+12.65dB
+12.65dB
+14.65dB
Table 53. SPK-Amp Gain
Default
AVDD HVDD SPKG1-0 bits
SPK-Amp Output (DAC Input = 0dBFS)
ALC bit = “0”
ALC bit = “1”
(LMTH1-0 bits = “00”)
00
3.30Vpp
3.11Vpp
3.3V
01
4.15Vpp (Note 40)
3.92Vpp
10
6.75Vpp (Note 40)
6.37Vpp (Note 40)
3.3V
11
8.50Vpp (Note 40)
8.02Vpp (Note 40)
00
3.30Vpp
3.11Vpp
5.0V
01
4.15Vpp
3.92Vpp
10
6.75Vpp (Note 40)
6.37Vpp (Note 40)
11
8.50Vpp (Note 40)
8.02Vpp (Note 40)
Note 40. The output level is calculated by assuming that output signal is not clipped. In actual case, output signal may be
clipped when DAC outputs 0dBFS signal. DAC output level should be set to lower level by setting digital
volume so that Speaker-Amp output level is 4.0Vpp (HVDD=3.3V) or 6.0V (HVDD=5V) or less and output
signal is not clipped.
Table 54. SPK-Amp Output Level
MS0478-E-01
- 60 -
2006/10