AK4343 Datasheet, PDF (72/98 Pages) Asahi Kasei Microsystems – Stereo DAC with HP/RCV/SPK-AMP

ASAHI KASEI
[AK4343]
Addr
03H
Register Name
Signal Select 2
Default
D7
D6
D5
D4
D3
D2
D1
D0
LOVL LOPS MGAIN1 SPKG1 SPKG0 MINL
0
0
0
0
0
0
0
0
0
0
MINL: Switch Control from MIN pin to Stereo Line Output or Receiver Output
0: OFF (Default)
1: ON
When PMLO bit is “1”, MINL bit is enabled. When PMLO bit is “0”, the LOUT/ROUT pins go to AVSS.
SPKG1-0: Speaker-Amp Output Gain Select (See Table 53)
MGAIN1: Input Gain Control (See Table 22)
LOPS: Stereo Line Output Power-Save Mode
0: Normal Operation (Default)
1: Power-Save Mode
LOVL: Stereo Line Output / Receiver Output Gain Select (See Table 46, Table 47)
0: 0dB/+6dB (Default)
1: +2dB/+8dB
Addr
04H
Register Name
Mode Control 1
Default
D7
D6
D5
D4
D3
D2
PLL3 PLL2 PLL1 PLL0 BCKO
0
0
0
0
0
0
0
DIF1-0: Audio Interface Format (See Table 17)
Default: “10” (Left jutified)
BCKO: BICK Output Frequency Select at Master Mode (See Table 11)
PLL3-0: PLL Reference Clock Select (See Table 5)
Default: “0000”(LRCK pin)
D1
DIF1
1
D0
DIF0
0
Addr
05H
Register Name
Mode Control 2
Default
D7
D6
D5
D4
D3
D2
D1
D0
PS1
PS0
FS3 MSBS BCKP FS2
FS1
FS0
0
0
0
0
0
0
0
0
FS3-0: Sampling Frequency Select (See Table 6 and Table 7.) and MCKI Frequency Select (See Table 12.)
FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode.
BCKP: BICK Polarity at DSP Mode (See Table 18)
“0”: SDTO is output by the rising edge (“↑”) of BICK and SDTI is latched by the falling edge (“↓”). (Default)
“1”: SDTO is output by the falling edge (“↓”) of BICK and SDTI is latched by the rising edge (“↑”).
MSBS: LRCK Polarity at DSP Mode (See Table 18)
“0”: The rising edge (“↑”) of LRCK is half clock of BICK before the channel change. (Default)
“1”: The rising edge (“↑”) of LRCK is one clock of BICK before the channel change.
PS1-0: MCKO Output Frequency Select (See Table 10)
Default: “00”(256fs)
MS0478-E-01
- 72 -
2006/10