AK4343 Datasheet, PDF (10/98 Pages) Asahi Kasei Microsystems – Stereo DAC with HP/RCV/SPK-AMP

ASAHI KASEI
[AK4343]
Parameter
min
typ
max
Units
Speaker-Amp Characteristics: DAC → SPP/SPN pins, ALC=OFF, AVOL=0dB, DVOL=0dB, R_L=8Ω, BTL,
HVDD=3.3V; unless otherwise specified.
Output Voltage (Note 17)
SPKG1-0 bits = “00”, −0.5dBFS (Po=150mW)
-
3.11
-
Vpp
SPKG1-0 bits = “01”, −0.5dBFS (Po=240mW)
3.13
3.92
4.71
Vpp
HVDD=5V, SPKG1-0 bits = “11”, 0dBFS (Po=1W)
3.13
3.92
4.71
Vpp
Line Input Æ SPP/SPN pins, HVDD=5V,
SPKG1-0 bits = “11”, −1.5dBV Input (Po=1.2W)
-
2.83
-
Vrms
S/(N+D)
SPKG1-0 bits = “00”, −0.5dBFS (Po=150mW)
-
60
-
dB
SPKG1-0 bits = “01”, −0.5dBFS (Po=240mW)
20
50
-
dB
HVDD=5V, SPKG1-0 bits = “11”, 0dBFS (Po=1W)
20
30
Line Input Æ SPP/SPN pins, HVDD=5V,
SPKG1-0 bits = “11”, −1.5dBV Input (Po=1.2W)
-
20
-
dB
-
dB
S/N (A-weighted)
80
90
-
dB
Load Resistance
8
-
-
Ω
Load Capacitance
-
-
30
pF
Speaker-Amp Characteristics: DAC → SPP/SPN pins, ALC=OFF, AVOL=0dB, DVOL=0dB, C_L=3µF, R_series=10Ω x
2, BTL, HVDD=5.0V; unless otherwise specified.
Output Voltage SPKG1-0 bits = “10”, 0dBFS
-
6.75
-
Vpp
(Note 17) SPKG1-0 bits = “11”, 0dBFS
6.80
8.50
10.20
Vpp
S/(N+D)
SPKG1-0 bits = “10”, 0dBFS
-
60
-
dB
(Note 18) SPKG1-0 bits = “11”, 0dBFS
40
50
-
dB
S/N
(A-weighted)
80
90
-
dB
Load Resistance (Note 19)
50
-
-
Ω
Load Capacitance (Note 19)
-
-
3
µF
Mono Input: MIN pin (AIN3 bit = “0”; External Input Resistance=20kΩ)
Maximum Input Voltage (Note 20)
-
1.98
-
Vpp
Gain (Note 21)
MIN Æ LOUT/ROUT LOVL bit = “0”
−4.5
0
+4.5
dB
LOVL bit = “1”
-
+2
-
dB
MIN Æ HPL/HPR
HPG bit = “0”
−24.5
−20
−15.5
dB
HPG bit = “1”
-
−16.4
-
dB
MIN Æ SPP/SPN
ALC bit = “0”, SPKG1-0 bits = “00”
−0.07
+4.43
+8.93
dB
ALC bit = “0”, SPKG1-0 bits = “01”
-
+6.43
-
dB
ALC bit = “0”, SPKG1-0 bits = “10”
-
+10.65
-
dB
ALC bit = “0”, SPKG1-0 bits = “11”
-
+12.65
-
dB
ALC bit = “1”, SPKG1-0 bits = “00”
-
+6.43
-
dB
ALC bit = “1”, SPKG1-0 bits = “01”
-
+8.43
-
dB
ALC bit = “1”, SPKG1-0 bits = “10”
-
+12.65
-
dB
ALC bit = “1”, SPKG1-0 bits = “11”
-
+14.65
-
dB
Note 17. Output voltage is proportional to AVDD voltage.
Vout = 0.94 x AVDD(typ)@SPKG1-0 bits = “00”, 1.19 x AVDD(typ)@SPKG1-0 bits = “01”, 2.05 x
AVDD(typ)@SPKG1-0 bits = “10”, 2.58 x AVDD(typ)@SPKG1-0 bits = “11” at Full-differential output.
Note 18. In case of measuring at SPP and SPN pins.
Note 19. Load impedance is total impedance of series resistance (R_series) and piezo speaker impedance at 1kHz in Figure
58. Load capacitance is capacitance of piezo speaker. When piezo speaker is used, 10Ω or more series resistors
should be connected at both SPP and SPN pins, respectively.
Note 20. Maximum voltage is in proportion to both AVDD and external input resistance (Rin). Vin = 0.6 x AVDD x Rin
/ 20kΩ (typ).
Note 21. The gain is in inverse proportion to external input resistance.
MS0478-E-01
- 10 -
2006/10