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AK4343 Datasheet, PDF (55/98 Pages) Asahi Kasei Microsystems – Stereo DAC with HP/RCV/SPK-AMP | |||
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ASAHI KASEI
[AK4343]
When RCV bit = â1â, LOUT/ROUT pins become RCP/RCN pins, respectively. Lch/Rch signal of DAC or
LIN2/RIN2/LIN3/RIN3 is output from the RCP/RCN pins which is BTL as (L+R)/2 signal. The load impedance is 32â¦
(min). When the PMLO bit = â0â, the mono receiver output enters power-down mode and the output is Hi-Z. When the
PMLO bit is â1â and LOPS bit is â1â, mono receiver output enters power-save mode. Pop noise at power-up/down can be
reduced by changing PMLO bit at LOPS bit = â0â. When PMLO bit = â1â and LOPS bit = â0â, mono receiver output
enters in normal operation. LOVL bit set the gain of mono receiver output.
DAC
âDACLâ
âLOVLâ
RCP pin
RCN pin
PMLO
0
1
Figure 48. Mono Receiver Output
LOVL
Gain
Output Voltage (typ)
0
+6dB
0.59 x AVDD @â6dBFS Default
1
+8dB
0.59 x AVDD @â8dBFS
Table 47. Mono Receiver Output Volume Setting
LOPS
Mode
RCP
RCN
x
Power-down
Hi-Z
Hi-Z
1
Power-save
Hi-Z
VCOM/2
0
Normal Operation Normal Operation Normal Operation
Table 48. Receiver-Amp Mode Setting (x: Donât care)
Default
PMLO bit
LOPS bit
RCP pin
Hi-Z
Hi-Z
RCN pin Hi-Z
VCOM
VCOM
Hi-Z
>1ms
>0
Figure 49. Power-up/Power-down Timing for Receiver-Amp
MS0478-E-01
- 55 -
2006/10
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